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Alberto Dei, Maurizio Valle
Modeling charge injection non-linear effects in Sigma-Delta Modulators using SIMULINK

Sigma-delta (ΣΔ) modulators are the most suitable A/D converters for low to medium frequencies, high-resolution applications, in view of their inherent linearity, reduced antialiasing filtering requirements and robust analog implementation. Moreover, the growing market for asymmetrical digital subscriber line (ADSL) applications is a driving force for the development of high speed, high resolution, sigma-delta analog-to-digital converters (ADC’s). In the wider development of ADC systems, a pre-eminent role has been played by modeling techniques. Modeling of ADC allows the device behavior to be predicted with a few of preventive experiments. For this reason, in the last years a great deal of scientific interest has been directed to ADC modeling.
In this work we present a SIMULINK model, which takes into account, for the first time, the non-linear effects due to switch charge injection in Sigma-Delta modulators. These effects are non-linearly proportional to the input voltage value. This brings about offset and harmonic distortion. Therefore adequate modeling of charge injection in terms of harmonic distortion is extremely important to predict and estimate the performance of Sigma-delta modulators.

Henrik Lundin, Mikael Skoglund, Peter Händel
Minimal Total Harmonic Distortion Post-Correction of ADCs

Dynamic digital post-correction of AD converters is considered. A generalized dynamic correction method is proposed and a framework for analyzing the related bit allocation problem is introduced. Finally, this framework is employed in an optimization problem. The solution to the problem indicates which ADC output bits to use in order to maximize the THD in a post-correction system with a constraint on memory size.
The proposed methods are accompanied by exemplary results obtained using experimental ADC data.

Andrea Sosso, Roberto Cerri
Compensation of Digital Voltmeters Nonlinearities by means of a Quantum Standard

The high linearity and stability of modern top-level Digital Voltmeters (DVM) can be exploited to measure voltage ratios with very low uncertainty by making two separate absolute voltage measurements. Yet, to obtain the very low uncertainties required to use a DVM as a voltage ratio standard, the intrinsic linearity of the instrument is not sufficient and techniques to determine and correct the residual non linearities must be adopted.
The Josephson Array Voltage Standard (JAVS) is well known as a voltage standard with nearly ideal accuracy. JAVS can can be also used for voltage ratio calibration, provided a source with high short- term stability is available. JAVS are then the best way to measure the very small linearities of a DVM, being the short-term requirement generally fulfilled by high quality voltmeters.
We performed several measurements for the evaluation of the linearity of DVMs in use in our laboratories, aimed at determining the performances of commercial multimeters as voltage ratio standards for the dissemination of the volt and for replacing ordinary techniques based on resistive dividers in primary metrology. The results appear to be encourag- ing for both applications: after calibration, uncertainty below 0.1 ppm can be obtained, with a stable profile of non linearity correction over time.

J. Halámek, I. Viščor, M. Kasal, M. Villa, P. Cofrancesco
Dynamic Nonlinearity at Undersampling, Fast ADC

In the undersampling applications the quality of sample-and-hold circuit is cardinal. The beat frequency and envelope tests made with identical input signal and identical form of output data may determine the errors given by SAH. The increased power of higher (from 10th to 50th) harmonics terms was the most significant marker of SAH imperfections in our measurement of AD6644.

Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, Soo Won Kim
2.5 V, 10-bit, 50-MS/s CMOS Pipeline Low Power A/D Converter

In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25 um CMOS process provides a resolution of 10bits at a sampling rate of 50 MS/s while dissipating 67 mW from 2.5 V supply voltage.
This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5 bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

Gil Su Kim, Hoon Jae Ki, Meejoung Kim, Soo Won Kim
Rail-to-Rail High Gain Telescopic Operational Amplifier Using Positive Feedback Technique

A CMOS very high DC-gain telescopic amplifier that uses internal positive feedback technique is presented. The structure of considered amplifier is consisted of rail-to-rail output swing and very high DC-gain. Simulation results predict a DC-gain can be achieved larger than 100 dB without limiting the output swing. The proposed amplifier is applied to sample and hold circuit for 10bits 100 Ms/s ADC.

Antonino S. Fiorillo , Gianni D’Angelo
A/D Convertion Error Propagation in Distance Measurement with a Sonar System based on Piezopolymer Sensors

The paper deals with the investigation on the propagation of the A/D convertion error during the distance measurement with an ultrasonic sensor aimed to emulate the behaviour of the bat bio-sonar.
In previous experiments the echo signals were processed with a 8 bit DSP and the target distance of 27 cm was evaluated with an accuracy of λ/50, but until now the nature of the measurement error was not verified.
The signal reconstruction algorithm should employ an inverse transfer characteristic with respect to that of the sensor. In the proposed application the propagation error is evaluated at different distances ranging from 27 cm to 200 cm (one-path way), by considering an ideal signal reconstruction block, which however processes the global convertion error. At the minimum distance the results are in good agreements with those one obtained in the experiments.

S. Marabelli, A. Fornasari, P. Malcovati, F. Maloberti
A 14-BIT BANDPASS MASH SIGMA-DELTA PIPELINE A/D CONVERTER

In this paper a two stage bandpass MASH (multi-stage noise shaping) sigma-delta (Σ∆) modulator is presented. A resolution of 14 bits has been achieved over a 5 MHz band around an intermediate frequency (IF) of 20 MHz with a clock frequency of 80 MHz. This performance is obtained using a 6-th order bandpass Σ∆ modulator followed by a 10 bit pipeline converter. The proposed circuit has been extensively simulated, both at behavioral and at circuit level, and results are illustrated.

T. Sumimoto, T. Maruyama, Y. Azuma, S. Goto, M. Mondou, N. Furukawa, S. Okada
Image Analysis Techniques for the Detection of Defects at BGA by X-Ray

This paper deals with the development of image analysis for the detection of defects at BGA solder joints in PC boards by using X-ray imaging. We can’t detect visually defects at BGA solder joints, because they are hidden under the IC package. To improve a cost performance and the reliability of PC boards, an inspection of BGA is required in the surface mount process. Types of defects at BGA solder joints are solder bridge, missing connection, solder voids, open connection and miss-registration of parts. As we can find mostly solder bridge in these defects, we pick up this to detect solder bridge in a production line. The problems of image analysis for the detection of defects at BGA solder joints are the detection accuracy and image processing time according to a line speed of production. To get design data for the development of the inspection system, which can be used easily in the surface mount process, it is important to develop image analysis techniques based on X-ray image data. At the first step of our study, we attempt to measure the shape of BGA based on X-ray imaging.

Takamoto Watanabe, Tamotsu Mizuno, Tomohito Terasawa, Sumio Masuda
An All-Digital A/D Converter for Increased Resolution With a 222-Delay-Unit TAD Architecture Using Moving-Average Filtering

An all-digital A/D converter (ADC) for increased resolution with a 222-delay-unit delay-line using TAD architecture [1] is presented. The basic structure of the TAD is a completely digital circuit including a ring-delay-line (RDL) with delay units (DUs) and a frequency counter, latch and encoder. The operating principle is to count the number of DUs through which the delay pulse passes within a sampling time. A 22-bit TAD area is 0.34 mm² (0.65-µm CMOS), and its resolution of 1 µV/LSB (1 kS/s) per (1.5-2.5 V) was realized with 20-bit resolution. Sample holds are unnecessary, and a low-pass filter function [1] removes high-frequency noise simultaneously with A/D conversion. On the other hand, low-frequency noise can be eliminated by using digital correction with this TAD. The likelihood is also suggested that TAD has no internal low-frequency noise.

Page 214 of 977 Results 2131 - 2140 of 9762