FULL FLASH LOGARITHMIC ADC ARCHITECTURE

Roberto Lojacono, Arianna Mencattini, Marcello Salmeri, Silvia Sangiovanni

Abstract

The advantages of a signal processing in the logarithmic domain are recently pointed out by some authors. On the other hand, suitable logarithmic input amplifiers are available in the literature. The traditional logarithmic amplifier configuration based on a voltage operational amplifier with a diode connected transistor in its feedback loop, which displays a significantly reduced bandwidth at lower signal levels, was modified replacing the operational amplifier by a transconductance feedback amplifier. This solution overcomes the said problem completely and offers constant-bandwidth operation throughout the full signal range. Some authors have proposed algorithmic architectures for the hardware realization of logarithmic Analogue to Digital Converters (ADC). This paper presents a fully analogue architecture of logarithmic ADC. The proposed architecture represents a logarithmic version of the calliper rule based linear ADC recently proposed. The main feature of this architecture is the small number of reference resistors needed, namely 3*2^n/2 instead of 2ⁿ, being n the number of bits of the binary converted sample.

Keywords

logarithmic ADC, subranging ADC, calliper rule

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PWC-2006-TC4-IWADC-013u.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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