OPTIMIZED DECIMATION STRUCTURE FOR COMPLEX BANDPASS ΣΔ MODULATOR IN WIDEBAND RECEIVER

Haifa FARES, Chiheb REBAI, Bertrand LE GAL, Dominique DALLET

Abstract

This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex bandpass ΔΣ modulator in wideband-standards receiver. The RF front-end has been based on a modified low-IF architecture and the full receiver dynamic range is converted into the digital domain. The approach proposed investigates a new decimation process and realizes new functionalities such as image rejection and frequency down conversion IF/DC by a complex mixing on ΣΔ modulator bit stream. Two wide standards (IEEE 802.11a and 802.16) were chosen for design procedure illustration. The decimation structure was implemented on FPGA component using optimization techniques. Experimental results show the highspeed data rate and low-power consumption features of the proposed design.

Download

IMEKO-IWADC-2008-095.pdf

DOI

-

IMEKO TC

TC4 - Measurement of Electrical Quantities

Back to the proceedings