MEASURING AND INTERPRETING THE CMOS IC VARIABLE INPUT IMPEDANCE VERSUS ESD STRESS

Alexandru Salceanu, Valeriu David, Mihai Cretu

Abstract

The paper presents a comparative method (and the related results) for measuring the various impedances of a Si-gate CMOS digital circuit, very useful for the study of the dual input protection configuration, with respect to an ESD pulse. The results of the performed measurements are interpreted according to the behaviour of the two main protective circuits and are useful to verify the waveform at the output of a self-manufactured ESD tester, the load values being essential.

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IMEKO-TC4-2004-092.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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