HARDWARE REDUCTION IN DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERS VIA BUS-SPLITTING
Abstract
This paper discusses a bus-splitting technique for hardware reduction in error feedback digital delta-sigma modulators (DDSMs). The technique is based on error masking and is applied to DDSMs with sinusoidal inputs. We consider the components that contribute to the output signal-to-noise ratio in conventional DDSMs and review new architectures for implementing the digital algorithms without sacrificing performance.
Event details
- Event
- IWADC 2011
- Technical Committee
- TC4
- Place
- Orvieto, ITALY
- Time
- 30 June 2011 - 1 July 2011
- Website
- http://www.iwadc2011.diei.unipg.it/Sito/IWADC2011.html