ULTRA COMPACT AND LOW-POWER TDC AND TAC ARCHITECTURES FOR HIGHLY-PARALLEL IMPLEMENTATION IN TIME-RESOLVED IMAGE SENSORS

David Stoppa, Fausto Borghetti, Justin Richardson, Richard Walker, Robert K. Henderson, Marek Gersbach, Edoardo Charbon

Abstract

We report on the design and characterization of three different architectures, namely two Time-to- Digital Converters (TDCs) and a Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion, implemented in a 130-nm CMOS imaging technology. The proposed circuit solutions are conceived for implementation at pixel-level, in image sensors exploiting Single-Photon Avalanche Diodes as photodetectors. The fabricated 32 × 32 TDCs/TACs arrays have a pitch of 50 µm in both directions while the average power consumption is between 28 mW and 300 mW depending on the architectural choice. The TAC achieves a time resolution of 160 ps on a 20-ns time range with a differential and integral non-linearity (DNL, INL) of 0.7 LSB and 1.9 LSB respectively. The two TDCs have a 10-bit resolution with a minimum time resolution between 50 ps and 119 ps and a worst-case accuracy of ±0.5 LSB DNL and 2.4 LSB INL. An overview of the performance is given together with the analysis of the pros and cons for each architecture.

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