Architecture of successive approximation time-to-digital converter with single set of delay lines

Dariusz Kościelnik, Jakub Szyduczyński, Dominik Rzepka, Wojciech Andrysiewicz, Marek Miśkowicz

Abstract

The paper addresses a time-to-digital conversion method based on successive approximation algorithm in time domain (SA-TDC). The SA-TDC is based on successive delaying the events defining a start and a stop of the input time interval being converted to a digital number by the use of binaryscaled delay components. The paper contribution is a presentation of several enhancements of SA-TDC architecture with single set of delay lines such as a reduction of hardware complexity and a decrease of quantization step by asymmetric inverter design in delay lines. On the other hand, the problem of metastability in logic appeared during conversion process for quasi-simultaneous inputs as a significant drawback of SA-TDCs is explored.

Keywords

time-to-digital converter, successive approximation, delay line, metastability

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IMEKO-TC4-2014-413.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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