Digital reconstruction stage of the FBD %Sigma;%Delta;-based ADC architecture for multistandard receiver

Rihab Lahouli, Manel Ben-Romdhane, Chiheb Rebai, Dominique Dallet

Abstract

This paper presents the design of a digital reconstruction stage for a frequency band decomposition (FBD)-based analog-to-digital converter (ADC) architecture for digitizing multistandard receiver signals. The proposed FBDbased ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4th order single-bit %Sigma;%Delta; modulators. The mixed baseband architecture uses a single non programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that proposed FBD architecture satisfies design specifications of the proposed software defined radio (SDR) receiver. In this paper, the authors focus essentially on the reconstruction stage design for UMTS use case while discussing digital stage processing and performances.

Keywords

Sigma-Delta Modulators, Frequency Band Decomposition, Parallel ADC

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IMEKO-TC4-2014-298.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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