MODELING OF ADC ARCHITECTURES IN HDL LANGUAGES

Marco Oliveira, Nuno Franca

Abstract

This paper describes the modeling of A/D converters in HDL languages such as Verilog [1] and VHDL[2]. It starts with an introduction about the importance of hardware modeling to support the flow of modern integrated circuit design, followed by the presentations of two case studies. The first case study is an A/D converter with successive approximations architecture [3][4][5]. The functional model was written in VHDL. The second case study is an A/D converter with pipelined architecture [3][4][6], whose functional model was written in Verilog.

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IMEKO-TC4-2001-140.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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