2.5 V, 10-bit, 50-MS/s CMOS Pipeline Low Power A/D Converter

Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, Soo Won Kim

Abstract

In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25 um CMOS process provides a resolution of 10bits at a sampling rate of 50 MS/s while dissipating 67 mW from 2.5 V supply voltage.<BR />This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5 bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

Keywords

Analog-to-digital converter, pipeline ADC, MDAC, switched-capacitor circuits, 1.5bit per stage

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DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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