POWER OPTIMIZATION OF HIGH-RESOLUTION LOW-BANDWIDTH SC ΔΣ MODULATORS

Serena Porrazzo, Francesco Cannillo, Chris van Hoof

Abstract

This paper presents a procedure for the power-optimal design of high-resolution low-bandwidth switched-capacitor (SC) &Delta;&Sigma; modulators (&Delta;&Sigma;Ms). The most power efficient &Delta;&Sigma; architecture is identified among single-loop switched-capacitor (SC) feedback (FB) and feed-forward (FF) topologies with different loop order <i>N</i>, oversampling ratio <i>OSR</i>, and quantizer resolution <i>B</i>. Based on the results obtained, an experimental prototype is implemented in a 0.18 µm CMOS process, achieving a signal-to-noise ratio (SNR) of 95 dB over a signal bandwidth <i>f</i>_BW of 10 kHz. The prototype operates with a 1.28 MHz sampling rate and dissipates a total power of 210 µW from a 1.8V supply.

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DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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