UTokyo VDEC’s CMOS-MEMS Technology via Nanotechnology Platform for Prospective Integrated Magnetic Sensor

Yoshio Mita, Eric Lebrasseur, Tomoki Sawamura, Naoko Kondo, Kunihiro Asada

Abstract

The paper summarizes CMOS-MEMS multi-project activities among the “Ultrafine Lithography and Nano Measurement Center” of Japanese Government of Education (MEXT)’s Nanotechnology Platform Program, participated by VLSI Design and Education Center of the University of Tokyo. The best mix and match of (1) CMOS LSI fabrication on user-defined Silicon on Insulator (SOI) wafer through VDEC’s multi-chip foundry service and (2) MEMS post-processing in cutting-edge micro/nano fabrication apparatuses installed in Federal Class 1 Supercleanroom of VDEC in Takeda Sentanchi Building provides powerful realization tool for brand-new microdevices research. The presentation includes introduction to the activities together with CMOS-MEMS microdevice examples and prospectives.

Keywords

Nanotechnology, MEMS, sensors

Download

IMEKO-TC4-2014-531.pdf

DOI

-

IMEKO TC

TC4 - Measurement of Electrical Quantities

Back to the proceedings