An All-Digital A/D Converter for Increased Resolution With a 2²²-Delay-Unit TAD Architecture Using Moving-Average Filtering

Takamoto Watanabe, Tamotsu Mizuno, Tomohito Terasawa, Sumio Masuda

Abstract

An all-digital A/D converter (ADC) for increased resolution with a 2²²-delay-unit delay-line using TAD architecture [1] is presented. The basic structure of the TAD is a completely digital circuit including a ring-delay-line (RDL) with delay units (DUs) and a frequency counter, latch and encoder. The operating principle is to count the number of DUs through which the delay pulse passes within a sampling time. A 22-bit TAD area is 0.34 mm² (0.65-µm CMOS), and its resolution of 1 µV/LSB (1 kS/s) per (1.5-2.5 V) was realized with 20-bit resolution. Sample holds are unnecessary, and a low-pass filter function [1] removes high-frequency noise simultaneously with A/D conversion. On the other hand, low-frequency noise can be eliminated by using digital correction with this TAD. The likelihood is also suggested that TAD has no internal low-frequency noise.

Keywords

ADC, moving average, all-digital

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IMEKO-IWADC-2003-20.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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