Effects of pipelined ADC architecture and Σ∆ modulator on Digital Down Conversion

D. Grimaldi, L. Serratore

Abstract

The paper reports on the investigation and simulation about the influence on the Digital Down Conversion (DDC) output signal of (i) the Σ∆ modulator, (ii) the pipelined ADC architecture and (iii) some relevant non-idealities of their model such as the sampling jitter, thermal noise and finite gain of the operational amplifier. The investigation is performed in the case that the digital filters of the DDC are in accordance with the GSM mask.

Keywords

Σ∆ ADC, pipelined ADC, Software Defined Radio

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IMEKO-IWADC-2003-47.pdf

DOI

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IMEKO TC

TC4 - Measurement of Electrical Quantities

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