This paper describes pipelined switched-current A/D converter designed in 0.6 µm BiCMOS technology. Modified conventional-restoring algorithm, called redundant-sign-digit (RSD), was implemented what decreases the amount of high-precision components. Two modes of operation are possible. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Proposed A/D converter is suitable for conversion of the current with very low amplitude from analog into digital domain. Current mode enables operation down to 3 V thus is suitable for...
In this paper we discuss some properties of different codes with their respective sets of weights to be used in digital-to-analog converters (DACs). The thermometer (unratioed) code is widely used instead of a binary code in the most significant bits of a segmented DAC to reduce errors due to weight and timing mismatch. The binary and thermometer codes are two extremes, where the first offers a small digital hardware cost and the latter a large cost. We have investigated some of the properties of these codes and codes with properties in-between; such as linear, polynomial, and segmented...
This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.
There exists a disproportionate difference between dynamic range, resolution, and accuracy when the output of sensors having nonlinear characteristics like thermistors are digitized with the conventional linear ADCs. There are several methods to linearise the thermistor characteristics but at the expense of hardware, memory and time efficiency. This paper presents a new simple method of shaping the transfer function of a pulse width modulation ADC as per the thermistor characteristics. It is based on the principle of varying the amplitude of the reference voltage to reach the temperature...
This paper investigates the effects of Integral Non-Linearity (INL) on the performances of both A/D converters and Digital Communication Systems, which exploit Direct Digital Modulation. The performances of both PCM and Sigma-Delta converters affected by INL are considered and compared. Then, the effects of INL upon the BER performances of an OFDM system are evaluated and modeled. The accuracy of the theoretical model is discussed with respect to the ADC resolution and INL levels. It is shown that a multibit Sigma-Delta converter, operating at a low oversampling ratio, may outperform PCM...
The growing demand of mixed–signal integrated circuits encourages the research of Built-In Self-Test (BIST) techniques to achieve simpler and less expensive testing processes. High quality sinusoidal oscillators based on a Δ-Σ topology are an effective solution to perform the test of this kind of devices. Unfortunately, due to the in–loop 1–bit quantizer nonlinearity, several problems of stability have been observed. A stability analysis on the behavior of the oscillator based on a second order Δ-Σ modulator presented in [1] is described in this paper. In particular, it is shown that the...
A fully digital algorithm is described for acquiring and correcting the errors of the feedback DAC used in a multibit ΔΣ MASH ADC. The method operates in the background and is highly accurate. It is particularly useful for wideband ADCs, where mismatch error shaping becomes ineffective. Combined with an improved digital adaptive compensation technique, which greatly reduces the raw quantization leakage in MASH architecture, it makes the design of fast and accurate ADCs using inaccurate components possible.
In this paper a new optimized multi-stage ΔΣ (Delta-Sigma) structure is proposed. The method combines the reduced-sample-rate architecture with the optimization of the zeros of the noise transfer function (NTF). To achieve this, the first stage of the decimation filter has to be modified as well. Applying this method one can avoid the SNR loss introduced by using the reduced-sample-rate second-stage. The SNR can actually increase for higher-order structures. Simulation results for a 2-0 MASH structure with an oversampling ratio of 4 are shown to verify the technique.
This paper presents an improved rnethod to digitally correct for statit, analog circuit imnperfections in a two-stage, 6 th order, cascaded (6-3) sigma-delta modulator. By adding a digital correction term to the output of die digital noise cancellation filter, the first stage parasitic quantization noise due to finite amplifier gain and C-Ratio mismatches can be completely removed. A 6-3 modulator implemented as a fully differential switched-capacitor circuit, designed for an OSR of 16, has heen fabricated in a 1.2 µm double-poly n-well CMOS process. Improvements have been made in the null...