The paper examines a behavioral model of sigma-delta analog-to-digital converters (SDADC) which allows the uncertainty of A/D conversion to be evaluated. The most sources of the uncertainty are represented in data sheets of modern SDADC. However, information given by manufacturers now is not enough to evaluate the conversion uncertainty with given probability. The most critical situation takes place for noise of SDADC − the major source of the uncertainty in many cases. This problem is mainly discussed in the paper. Conditions for evaluation of the conversion uncertainty with given...
The standard DC parameters of an Analog to Digital converter (ADC) are linearity (integral and differential), offset and gain. To test these parameters, the voltage needs to be measured, as the output of the ADC changes from one code to the next code (transition voltage). For example, the unipolar zero of an ADC is specified as the voltage of the first code transition (code 0 to code 1) minus the respective voltage of half a LSB (least significant bit). This article compares different test solutions.
A switched-capacitor bandpass analog-to-digital-converter is one of the circuit blocks used in wireless communication systems to digitize the re- ceived analog signal at certain center frequency ( f c ). This particular con- verter is used especially for digital FM or AM radio applications and most of the portable communication devices such as cellular-phones. The main block of this converter is the resonator, which resonates at this f c center frequency. Two of the main design criteria of the resonators are; to have very high quality resonance peak and to locate the center frequency ac-...
A low-voltage and low-power bandpass ∆Σ modulator is described. In this design, two novel ideas are incorporated: unity-gain-reset and integrating-two-path techniques. A test chip, realized in a 0.35- µ m CMOS process and clocked at both 20 and 40 MHz, provided a dynamic range DR = 45 dB and a signal-to-noise+distortion-ratio SNDR = 36 dB for a 100-kHz signal bandwidth at 5MHz center frequency, and DR = 30 dB and SNDR = 32 dB for a 200-kHz BW at 10MHz center frequency. The supply voltage was 0.8 V for 20 MHz clock, and 0.9 V for 40 MHz clock.
The analog to digital converter is one of the key devices for future receiver design taking into account performance and cost. Is this dream for true software radio applications ( within certain conditions) achievable in a few years ? Developing such application will mean very high analog input intermediate frequency with wide bandwidth to be converted with very low spurious intermodulation (much better than – 85 db) translating to 12..14 bit resolution ADC sampled at very high clock rates. Modeling of such a specification gives special restriction on the choice of the ADC architecture and...
This paper presents design considerations for ΣΔMs aimed at high-linearity, high-speed A/D conversion. We analyze the performance of a family of high-order cas- cade multi-bit architectures in a low-voltage, deep-sub- micron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are promising candidates to achieve post-ADSL performances in future CMOS processes.
In this paper a novel method for the on-line calibration of the DAC used in multi-bit sigma-delta modulators is described. The proposed solution uses an additional trans- mission zero in the noise transfer function located at half of the sampling frequency. The mismatch between each unity element and a reference is properly modulated and located at the notch position. Since the notch frequency is noise free a simple digital processing allows us to measure mismatches and to store them in a digital memory for digital calibration purposes. The paper shows how to practically implement the...
The linearity of higher order Σ-Δ modulator using MOSFET capacitors is examined. Two 3 rd -order network structures are investigated. For low-voltage power supplies with reference voltages under 1 volt, the performance of a MOSFET-only modulator is predicted to be very close to that of a modulator using linear capacitors. It is possible to realize similar performance in selected modulator network structures. We investigate the performance of a 2-1 cascade and a 3 rd -order iflf topology in a 0.35 µm process.
In this paper a new structure for a band-pass sigma delta modulator is proposed. The center frequency of the modulator can be tuned in the range between DC to half the sampling frequency by means of only one parameter. The modulator stability and the nearly constant resolution for the whole frequency range are demonstrated.
Cascaded sigma-delta converters relax the requirements on the oversampling ratio for a given resolution, but their performance is sensitive to imperfections in the analog components. Previous work has focussed on adaptive calibration schemes to address this problem. In contrast, the main contribution of the present work is the development of a framework for the synthesis of robust digital correction filters that provide a guaranteed level of performance for the worst case uncertainty in parameter values. The validity of the approach is established by successfully reproducing well-known...