Alberto Dei, Maurizio Valle
Sigma-delta (ΣΔ) modulators are the most suitable A/D converters for low to medium frequencies, high-resolution applications, in view of their inherent linearity, reduced antialiasing filtering requirements and robust analog implementation. Moreover, the growing market for asymmetrical digital subscriber line (ADSL) applications is a driving force for the development of high speed, high resolution, sigma-delta analog-to-digital converters (ADC’s). In the wider development of ADC systems, a pre-eminent role has been played by modeling techniques. Modeling of ADC allows the device behavior to...
Henrik Lundin, Mikael Skoglund, Peter Händel
Dynamic digital post-correction of AD converters is considered. A generalized dynamic correction method is proposed and a framework for analyzing the related bit allocation problem is introduced. Finally, this framework is employed in an optimization problem. The solution to the problem indicates which ADC output bits to use in order to maximize the THD in a post-correction system with a constraint on memory size. The proposed methods are accompanied by exemplary results obtained using experimental ADC data.
Andrea Sosso, Roberto Cerri
The high linearity and stability of modern top-level Digital Voltmeters (DVM) can be exploited to measure voltage ratios with very low uncertainty by making two separate absolute voltage measurements. Yet, to obtain the very low uncertainties required to use a DVM as a voltage ratio standard, the intrinsic linearity of the instrument is not sufficient and techniques to determine and correct the residual non linearities must be adopted. The Josephson Array Voltage Standard (JAVS) is well known as a voltage standard with nearly ideal accuracy. JAVS can can be also used for voltage ratio...
J. Halámek, I. Viščor, M. Kasal, M. Villa, P. Cofrancesco
In the undersampling applications the quality of sample-and-hold circuit is cardinal. The beat frequency and envelope tests made with identical input signal and identical form of output data may determine the errors given by SAH. The increased power of higher (from 10 th to 50 th ) harmonics terms was the most significant marker of SAH imperfections in our measurement of AD6644.
Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, Soo Won Kim
In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25 um CMOS process provides a resolution of 10bits at a sampling rate of 50 MS/s while dissipating 67 mW from 2.5 V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5 bit per stage MDAC with switched capacitors...
Gil Su Kim, Hoon Jae Ki, Meejoung Kim, Soo Won Kim
A CMOS very high DC-gain telescopic amplifier that uses internal positive feedback technique is presented. The structure of considered amplifier is consisted of rail-to-rail output swing and very high DC-gain. Simulation results predict a DC-gain can be achieved larger than 100 dB without limiting the output swing. The proposed amplifier is applied to sample and hold circuit for 10bits 100 Ms/s ADC.
Antonino S. Fiorillo , Gianni D’Angelo
The paper deals with the investigation on the propagation of the A/D convertion error during the distance measurement with an ultrasonic sensor aimed to emulate the behaviour of the bat bio-sonar. In previous experiments the echo signals were processed with a 8 bit DSP and the target distance of 27 cm was evaluated with an accuracy of λ/50, but until now the nature of the measurement error was not verified. The signal reconstruction algorithm should employ an inverse transfer characteristic with respect to that of the sensor. In the proposed application the propagation error is evaluated at...
S. Marabelli, A. Fornasari, P. Malcovati, F. Maloberti
In this paper a two stage bandpass MASH (multi-stage noise shaping) sigma-delta (Σ∆) modulator is presented. A resolution of 14 bits has been achieved over a 5 MHz band around an intermediate frequency (IF) of 20 MHz with a clock frequency of 80 MHz. This performance is obtained using a 6-th order bandpass Σ∆ modulator followed by a 10 bit pipeline converter. The proposed circuit has been extensively simulated, both at behavioral and at circuit level, and results are illustrated.
T. Sumimoto, T. Maruyama, Y. Azuma, S. Goto, M. Mondou, N. Furukawa, S. Okada
This paper deals with the development of image analysis for the detection of defects at BGA solder joints in PC boards by using X-ray imaging. We can’t detect visually defects at BGA solder joints, because they are hidden under the IC package. To improve a cost performance and the reliability of PC boards, an inspection of BGA is required in the surface mount process. Types of defects at BGA solder joints are solder bridge, missing connection, solder voids, open connection and miss-registration of parts. As we can find mostly solder bridge in these defects, we pick up this to detect solder...
Takamoto Watanabe, Tamotsu Mizuno, Tomohito Terasawa, Sumio Masuda
An all-digital A/D converter (ADC) for increased resolution with a 2 22 -delay-unit delay-line using TAD architecture [1] is presented. The basic structure of the TAD is a completely digital circuit including a ring-delay-line (RDL) with delay units (DUs) and a frequency counter, latch and encoder. The operating principle is to count the number of DUs through which the delay pulse passes within a sampling time. A 22-bit TAD area is 0.34 mm² (0.65-µm CMOS), and its resolution of 1 µV/LSB (1 kS/s) per (1.5-2.5 V) was realized with 20-bit resolution. Sample holds are unnecessary, and a low-pass...