Architecture of successive approximation time-to-digital converter with single set of delay lines |
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| Dariusz Kościelnik, Jakub Szyduczyński, Dominik Rzepka, Wojciech Andrysiewicz, Marek Miśkowicz |
- Abstract:
- The paper addresses a time-to-digital conversion method based on successive approximation algorithm in time domain (SA-TDC). The SA-TDC is based on successive delaying the events defining a start and a stop of the input time interval being converted to a digital number by the use of binaryscaled delay components. The paper contribution is a presentation of several enhancements of SA-TDC architecture with single set of delay lines such as a reduction of hardware complexity and a decrease of quantization step by asymmetric inverter design in delay lines. On the other hand, the problem of metastability in logic appeared during conversion process for quasi-simultaneous inputs as a significant drawback of SA-TDCs is explored.
- Keywords:
- time-to-digital converter, successive approximation, delay line, metastability
- Download:
- IMEKO-TC4-2014-413.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Symposium 2014
- Title:
20th IMEKO TC4 Symposium on Measurements of Electrical Quantities (together with 18th TC4 International Workshop on ADC and DCA Modeling and Testing, IWADC)
"Research on Electrical and Electronic Measurement for the Economic Upturn"- Place:
- Benevento, ITALY
- Time:
- 15 September 2014 - 17 September 2014