Response surface-based design of standard inductances for minimizing parasitic capacitances |
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| Pasquale Arpaia, Luca Sabato |
- Abstract:
- A procedure for reducing both deterministic and uncertainty effects of parasitic capacitance in designing standard inductors is presented. Metrological performance is enhanced while minimizing both deterministic and uncertainty effects simultaneously. In particular, statistical parameter design is exploited, by choosing optimum levels of design variables of the standard inductor. At this aim, initially, a first model is identified in order to define the impact of design parameters on parasitic capacitances considered as deterministic and the configuration for their minimization. Then, in the optimum configuration, a second model defines the impact of the design parameter uncertainty on the parasitic capacitance considered as random in order to assess the corresponding uncertainty budget. The method effectiveness is highlighted by a case study related to the design of an Ironless Inductive Position Sensor (I2PS).
- Keywords:
- inductor, parasitic capacitance, response surface
- Download:
- IMEKO-TC4-2014-996.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Symposium 2014
- Title:
20th IMEKO TC4 Symposium on Measurements of Electrical Quantities (together with 18th TC4 International Workshop on ADC and DCA Modeling and Testing, IWADC)
"Research on Electrical and Electronic Measurement for the Economic Upturn"- Place:
- Benevento, ITALY
- Time:
- 15 September 2014 - 17 September 2014