MODELING OF ADC ARCHITECTURES IN HDL LANGUAGES
Marco Oliveira, Nuno Franca
Abstract:
This paper describes the modeling of A/D converters in HDL languages such as Verilog [1] and VHDL[2]. It starts with an introduction about the importance of hardware modeling to support the flow of modern integrated circuit design, followed by the presentations of two case studies. The first case study is an A/D converter with successive approximations architecture [3][4][5]. The functional model was written in VHDL. The second case study is an A/D converter with pipelined architecture [3][4][6], whose functional model was written in Verilog.
Download:
IMEKO-TC4-2001-140.pdf
DOI:
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Event details
IMEKO TC:
TC4
Event name:
TC4 Symposium 2001
Title:

11th IMEKO TC4 Symposium on Trends in Electrical Measurements and Instrumentation (together with 6th IMEKO TC4 Workshop on ADC Modelling and Testing)

Place:
Lisbon, PORTUGAL
Time:
13 September 2001 - 14 September 2001
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