FLASH CALIPER SUBRANGING ARCHITECTURE |
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| R. Lojacono, A. Lordi, A. Mencattini, M. Salmeri |
- Abstract:
- The paper presents a subranging version of an already presented architecture based on a electrical transfer of the well known technique used to improve the accuracy of length measurements, namely the “nonio”. The particular feature of this last architecture is that greatly reduces the requested voltage reference levels that are necessary for the whole conversion. This in turn reduces the number of the requested resistors which, in an integrated realization, must have a great area to reduce the dispersion of the resistor values due to the alignment errors of the masks. Unfortunately this technique not reduces the number of the requested comparators. The subranging structure, widely used to reduce the number of comparators in the flash ADC architectures, is here adopted to reduce the number of comparators and implemented without performing the folding of the input signal to be converted. This last common practice is here avoided and replaced by an use of a mobile voltage reference scale of the some kind of the mobile scale requested by the electrical nonio implementation. The result is a very compact architecture.
- Download:
- IMEKO-IWADC-2011-55.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- IWADC 2011
- Title:
16th IMEKO International Workshop on ADC Modeling and Testing - Data Converter Design, Modeling and Testing (together with IEEE ADC Forum) (IWADC)
- Place:
- Orvieto, ITALY
- Time:
- 30 June 2011 - 01 July 2011