Architecture of the Multi-Tap-Delay-Line Time-Interval Measurement Module Implemented in FPGA Device |
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| Marek Zielinski, Maciej Gurski, Dariusz Chaberski |
- Abstract:
- This paper describes architecture of the Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in single FPGA device. A new architecture of the measurement module enables to collect of sixteen time-stamps during single measuring cycle. It means that measured time-interval can be precisely interpolated from collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads straight to increase of resolution, to limit total duration time of the measurements and to decrease of duty cycle of the measurement instrument.
- Keywords:
- time-interval measurements, time-stamps, delay line
- Download:
- IMEKO-TC4-2013-041.pdf
- DOI:
- -
- Event details
- IMEKO TC:
- TC4
- Event name:
- TC4 Symposium 2013
- Title:
- 19th IMEKO TC4 Symposium Measurements of Electrical Quantities (together with 17th TC4 IWADC Workshop on ADC and DAC Modelling and Testing)
- Place:
- Barcelona, SPAIN
- Time:
- 18 July 2013 - 19 July 2013