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Domenico Luca Carnì, Domenico Grimaldi, Leonardo Serratore
Time and Frequency Domain Tests for ΣΔ Modulators

The paper deals with the classification method of some architectures of ΣΔ modulators. The classification is based on the analysis of the different trends of the output signals characterizing some ΣΔ modulator architectures. The method operates (i) by feeding the ΣΔ modulator with sinusoidal signal, and (ii) by analysing the output signals in the time or in the frequency domain. The classification consists in (i) distinguishing between low pass and band pass ΣΔ modulator, (ii) identifying both the Single Quantizer Loop (SQL) and the Multistage Noise Shapers (MASH) architecture, (iii) evaluating the levels of the quantizer block inside the SQL architecture, and (iv) detecting the number of cascaded stage inside the MASH architecture. In order to validate the proposed method, numerical tests are performed by referring to the noumerous architectures of ΣΔ modulators proposed in the relevant literature.

F. Castelli, M. Faifer
The Voltage to Frequency Converter Using as Reference the Pull-In Voltage of a Reed Relay

The chief requirements of basic components of digital systems for industry are both the availability of preventive maintenance and high reliability. Integrated semiconductor components are highly lacking in both these requirements. To respond to the referred exigencies a voltage to frequency converter (VFC) by the use of a reed relay (RR) and a charge-discharge method with as reference the pull-in voltage of RR is illustrated. Test results prove a high linearity and that it is imperious to environmental temperature and proper for extreme environmental industrial conditions.

Martin Kollár, Linus Michaeli, Ján Šaliga
Parameters of Band Pass ΣΔ ADC and the Comparison with the Standard Ones

The bandpass sigma delta analog-digital converters (BP ΣΔ-ADC) represent a subgroup from the more general group of the unconventional ADCs. The BP ΣΔ-ADCs are mostly embedded into digital communication systems (DCS) in various applications. Their main task is to provide a frequency down conversion along with the conversion of chosen parameter of analog signal into digit. These converters are analog front end for DCS like software radios, UMTS, GSM and GPS systems. Parameters for characterisation of BP ΣΔ-ADC are until now taken intuitively and they are different from the standard conventional ADCs. The paper reviews existing parameters for conventional ADC with the aim to midificate them for BP ΣΔ-ADC.

Konrad Jędrzejewski, Anatoliy A. Platonov
Modelling and Analysis of Influence of Internal Converters Nonlinearity in Adaptive Cyclic A/D Converters

The paper focuses on modelling and analysis of influence of internal converters nonlinearities in sub-optimal intelligent cyclic A/D converters (IC ADC) whose backgrounds and architecture were presented and analysed in works [1-5] and others. The knowledge of influence of internal A/D converter nonlinearities errors on IC ADC conversion performance enables determining requirements for ADCIn which are of crucial importance for design and practical implementation of IC ADC.

Linus Michaeli, Peter Michalko, Jan Šaliga
Identification of Unified ADC Error Model by Triangular Testing Signal

Modelling of the integral nonlinearity by the unified behavioural error model expressed as one dimensional image in the code k domain requires a minimal number of the error parameters. The unified error model consists of low and high code frequency components. This paper presents a new approach how to determine the parameters of the low code frequency component by the same signal, that was proposed earlier for determining the high code frequency component. The authors prove that the triangular testing signal with exact DC component allows determining the model parameters with a sufficient accuracy.

N. Björsell, O. Andersen, P. Händel
High Dynamic Range Test-Bed for Characterization of Analog-to-Digital Converters up to 500 MSPS

A measurement set-up of for the characterization of analog-to-digital converters (ADCs) is described. The measurement set-up characterizes ADCs up to 16 bits at 350 MHz (option for >500 MHz). Testing dynamic performance of high-speed ADCs is regarded as difficult and expensive. By using existing state-of-the-art instruments in combination with specially designed amplifiers and filters, a high performance, cost efficient test-bed has been built-up. Practical performance corresponds to ADC datasheet and exceeds the performance obtained if using commercial instruments only. Consequently, the measurement results represent the true performance of the ADC without impact from the test-bed.

Anatoliy Platonov, Łukasz Małkiewicz
Direct and Indirect Methods of ENOB Evaluation and Analysis

The paper presents the backgrounds of analytically grounded approach enabling strict theoretic and experimental analysis of the cyclic analogue-to-digital converters (CADC) [1,2] performance. Methods of assessment of the effective number of bits (ENOB [3,4]) and effective resolution (EFR, [5]) of these converters are considered. The analysis is based on results of works [6-8] and develops the direct approach to real ENOB values evaluation proposed in [9]. There is shown the specific for CADC and important for design and applications effect of normalisation of the output quantization noise with the growth of the number of cycles.

F. Attivissimo, N. Giaquinto, A. M. L. Lanzolla, M. Savino
Coupling Dithering and Static Linearization in A/D Converters

This paper presents a study of the performance attainable by combining two different methods of linearization algorithms for A/D converters: dithering (which removes errors due to quantization) and static look-up table (which removes errors due to INL). The theory and the simulation results show two very important facts, i.e.: (i) the amplitude of the dither signal must be chosen according to the INL of the converter, and should be greater than the usual value of 0.5 LSB rms; (ii) using both the linearization techniques allows one to attain (in absence of other sources of error) an arbitrary high number of effective bits, proportional to the logarithm of the averaged samples.

A.A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret
Continuous-Time Delta-Sigma Modulator Model for A/D Conversion

In this paper we present a study of a Continuous-Time Delta-Sigma Modulator (CT ΔΣM) to be applied in radio communication systems, including a high-level modelization for simulation purposes. The conventional sample-and-hold and comparator blocks, very popular in CT ΔΣM models, are replaced by an analog-to-digital converter (ADC), in order to allow the ADC modelization. In this way, we propose a model able to improve the performances of ADCs. This model is a useful tool to characterize data conversion systems.

Maher Jridi, Rafael Shirakawa, Dominique Dallet
Aperture Jitter and Timing Skew Analyses in ADC Structure

Time interleaved ADCs are generally very sensitive to any sampling time errors. In order to study its influence in term of performance decreasing, there is introduced an ADC jitter model developed in Simulink. Simulation results of this model correspond with the formulas described in literature[1] and [2]. Timing skew errors of the time interleaved structure are discussed and compared to those of a single ADC.

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