The conversion rate of purely electronic analog-to-digital converters is limited in speed to conversion rates of some Gsps. A way to obtain substantially higher conversion rates is the use of photonic circuits as input stage of an analog-to-digital converter. A comparison of different approaches for optical analog-to-digital conversion is given with special emphasis on the properties of the key optoelectronic components employed in the different concepts. In particular we report the state of the art of the development of optoelectronic modulators, Self-Electrooptic-Effect-Devices and photodiodes and discuss the limitations imposed by the device properties to the conversion schemes.

The increasing complexity o f data converter architectures m akes it necessary to use behavioral m odels to simulate the electrical performances and to determine the relevant data converter features. For this purpose, special input stimulus and specific output data processing are required. Thus, we need a specific data-converter simulation environment. A iming at this objective, this paper analyses the m ost utilized a rchitectures and identifies the basic (active and passive) building blocks used. Behavioral m odels o f such basic blocks are discussed. The proposed behavioral m odels are then used in a pipeline and a sigma-delta converter. Specific routines for the determination of data converter parameters are presented. Simulations show that in addition to the analysis of limits and the electrical features extraction designer can determine the basic b locks specification that permit to m et given data converter requirements.

For dynamic quality tests of the AD converters a high quality test signal is required. When testing a high speed AD converters, the conventional test signals have reached their dynamic and resolution limits. In this paper an overview of using the step-wise approximated multi-cycle sine wave as a test signal for dynamic quality tests of high speed, high quality AD converters is presented. The proposed test signal is characterised by high stability time and amplitude parameters. The slight difference in the heights of steps of the sequential single cycles ensures stimulation of all codes of the AD converter. Basic rules for increasing the accuracy of the spectrum component evaluation by FFT analysis are considered.

Discretisation error is responsible for one of major metrological problems concerning digital instruments such as AD converters. Designing the device of stable relative error would provide the ideal solution. The aim of this work is to introduce the problem and propose the float point AD converter with variable gain amplifier (VGA) as a solution.
The proposed fast setting gain with flash AD converter as a coarse one is the new approach. The conversion consists of two stages coarse and fine one. The VGA works as pre-processing circuit for fine conversion. The VGA gives the stable signal value according to the coarse conversion. In result the relative error of conversion is stable. Programmable correction of the gain will be presented. The results of simulation confirm the measurement error stabilisation and high frequency operation.

Reducing interval arithmetic enables to describe properties of error sources in the matrix form. It is especially significant when algorithms process long measuring result sequences. Changes in time of measured quantity cause dynamic errors in the analog elements of measuring chain. When signal is nonsinusoidal the dynamic error can be presented as a set of harmonics. Those harmonics should be composed in order to get the resultant error. The method described in the paper enables to represent a set of harmonics as a set of intervals. The interdependence of those intervals is determined by the harmonics phase shifts. The method enables to calculate the amplitude of the harmonics sum in an approximate but simple way. The dynamic error amplitude calculated in the way described above is interpreted as a partial dynamic uncertainty of the measuring results. It can be composed with another kinds of partial uncertainties by using reducing arithmetic that enable to determine the final processing uncertainty.