The accuracy of instruments for measurement a magnetic induction depends on a multiplication error of a sensor. It is considered the new algorithms of this error reducing by mean of a pilot signal with uninterrupted and periodic comparison and also with the negative feedback with respect to envelope of signals.

The idea of acquiring not the proper samples at the input of an ADC but the difference ("Delta" and its sign "Sigma") between the new sample and the previous one (the derivative of the signal, in finite-difference sense) led to an important decrease of samples’ dynamic, provided the over-sampling frequency goes towards the slew-rate of the conversion circuits divided by the last significant bit. Considering the previous sample as the simplest (1-st order) estimate of the new sample, the authors modeled a more efficient way (in terms of speed and memory requirements): the acquisition of the difference between the new sample and a better estimate of it (higher order estimate, adapted to signal’s statistic).
The Levinson-Durbin algorithm is justified and implemented into an Itakura lattice. Computational similarities with the Schur-Cohn tests of stability are underlined. The authors implemented this computation scheme in a LabView “virtual ΣΔ ADC”.
Modelling by Mason graphs of the Itakura finite-impulse-response (FIR) of the predictive ΣΔ-ADC is followed by its symmetric flow-graph for the infinite-impulseresponse (IIR) DAC.

A calibration method for a system designed to measure complex voltage ratios is presented. The method is based on the application of an AC transformer bridge. The system comprises a multichannel data acquisition board with simultaneous sampling, input adaptation circuits and dedicated software. An analysis of the accuracy of the proposed calibration method is made. Experimental tests of the calibration system were performed for signals differing in phase by π/2 and π at frequencies from 50 Hz to 1 kHz.

Switched Current (SI) is a very interesting analog technique to perform interface circuits in mixed analog/digital systems because it is compatible with a low cost digital CMOS process (single poly technologies). The attempt of this work is to shed some light on the SI delta-sigma converter design method making use of an analog Hardware Description Language. To demonstrate the performances of the HDL-A model to optimize delta-sigma converters, a first order SI delta-sigma modulator has been designed, simulated and implemented using a 0.7 mm CMOS digital process. Also we have compared the simulated results and the experimental.

In this paper a novel approach for the direct computation of the probability density function (pdf) at the output of generic memory-less nonlinear processing blocks is derived. This method has been applied to the modeling of the THA-ADC chain. By using this approach, we are able to determine the exact behavior of the Signal to Noise Quantization Ratio (SQNR) of the THA-ADC chain for cases where the well-known Pseudo Quantization Noise (PQN) model do not give accurate results. The model can be easily improved to take into account for the ADC non idealities such as saturation and nonlinearity effects.