IMEKO Event Proceedings Search

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Olli Aumala
NETWORKING FOR MEASUREMENT EDUCATION

IMEKO TC1 has started a series of On Line (virtual) Workshops and a Portal for joint use of educational material. The aim of this activity is to help educators in organizing good co-operation and getting benefit of synergy in their work. The educators’ work includes classroom teaching and supervising of students, but also developing and collecting educational material, and preparing textbooks, lecture notes, exercise collections, demonstrations, etc. for educational use. Transferring new scientific results into a new form suitable for education is not a minor duty. The paper presents experience from the first Workshop and discusses needs, difficulties and methods in development of networking.

Roland Holcer, Linus Michaeli
TESTING DNL AND INL OF ADC BY THE EXPONENTIAL SHAPED VOLTAGE

Testing of ADC’s differential nonlinearity DNL(k) by the histogram method requires the signal generator with extremely low distortion and high stability of the parameters. Besides this condition generator must be connected to the input of the ADC under test with high suppression of the interfering noise on ground line of instruments. The new type of testing signal has been proposed of the exponential form which could be generated by discharging of the capacitor across the resistance. The acquired digital samples from the output of ADC under test allow determining the best fitted exponential signal. The histogram from the registered samples and that for the best fitted exponential shape allows determining the differential nonlinearity DNL(k) for any code level k. Practical problems with generating the pure exponential shape are shown in this paper. The proposed method has been experimentally verified and was compared with the standardized methods.

M. Comte, F. Azaïs, S. Bernard, Y. Bertrand, M. Renovell
ON THE EVALUATION OF ADC STATIC PARAMETERS THROUGH DYNAMIC TESTING

Full characterization of ADC requires both a histogram-based approach and a spectral analysis to determine respectively static and dynamic parameters. This paper investigates whether static performances can be extracted from spectral analysis, in order to develop a low-cost test procedure. Results show that under appropriate test conditions, the dynamic parameters extracted from a classical FFT exhibit significant variations against ADC offset and gain errors.

J. Halámek, I. Višèor, M. Kasal, M. Villa, P. Cofrancesco
HARMONIC DISTORTION AND STATISTICAL ANALYSIS

The measurement of harmonics terms on two identical digital receivers with fast ADC (AD6644) is presented and statistically analyzed. The results are discussed according to the origin of harmonics and difference between spurious and harmonics.

Carsten Wegener, Michael Peter Kennedy
TESTING ADCs FOR STATIC AND DYNAMIC NONLINEARITIES - KILLING TWO BIRDS WITH ONE STONE

Traditionally, static linearity and dynamic distortion tests are performed separately for ADCs. To this end, a low-frequency sinewave is histogrammed to measure static Integral Nonlinearity, and a high-frequency sine-wave is sampled for FFT processing to measure dynamic distortions and dynamic range.
We propose to use a model-based technique to extract both static and dynamic nonlinearities from a single data record of a sampled high-frequency sine-wave. This saves test time as the ADC converts fewer samples.

Ivo Viščor, Josef Halámek
ACQUISITION SYSTEM WITH LOW JITTER

The high dynamic range system is often limited by the jitter. The sources of the jitter are the clock generator, the clock distribution and the ADC. Two different methods of the ADC jitter measurement are presented.

Olli Vainio
ADAPTIVE SCHEME FOR OVERSAMPLED FRONT ENDS

A computationally efficient adaptive filtering scheme for oversampled A/D converters is discussed. The decimating digital filter is constructed as a combination of a sinc decimator and an adaptive predictor. A reduced-rank adaptive algorithm with two adaptive parameters is proposed for this purpose avoiding the complexity of the commonly used full-rank algorithms. The characteristics of the adaptive filter are considered, and a comparative example of data signal processing is shown.

G.C. Cardarilli, A. Del Re, R. Lojacono, A. Nannarelli, M. Re
PERFORMANCE COMPARISON BETWEEN TRADITIONAL AND RNS-BASED ADC

Recently a new architecture for an analog to Residue Number System converter was proposed by the authors. In this paper a comparison of the performances, in terms of probability of LSB error due to internal noise, between a traditional ADC converter and this said analog to RNS converter is given.

Reinhard Kindt, Richard Ižák
AN ANALOG APPROACH TO COMPENSATE FOR OpAmp OFFSET AND FINITE GAIN IN SC CIRCUITRY: A CASE STUDY OF A CYCLIC RSD ADC

Design of high-resolution Nyquist rate A/D converter necessitates the usage of advanced circuit techniques to compensate for arising analog errors. In switched capacitor ADC, besides the well know techniques such as bottom plate sampling, mismatch-independent and redundant (RSD: 1.5 bit/stage) conversion for the elimination of charge injection, capacitor mismatch, comparator and offset sensitivity, respectively, the most utilised circuit techniques are those for OpAmp’s offset and finite gain errors cancellation. An alternative technique for compensation of the errors due to finite gain and offset of Opamp in SC circuits is proposed. This novel method features a charge addition and is compared to so far used approaches based on voltage addition. The concept and the results of a 5 V CMOS implementation of cyclic RSD ADC with ratio-independent SC technique using this correction method are discussed.

Alberto Die, Maurizio Valle
EVALUATION OF TIME RESOLUTION OF NMOS SAMPLING SWITCHES

Usually in CMOS line receivers and downconversion mixers, a key component is the NMOS sampling switch. When designing sampling switches, one has usually to trade off resolution against bandwidth and aperture time. In this perspective, we modeled the aperture time of the NMOS sampling switch for low swing voltage signals taking also into account the dependence of the threshold voltage on the body effect. Then we compared the aperture time behaviour using three submicron CMOS technologies (0.8, 0.5 and 0.25 μm minimum channel length respectively). The results indicate that an aperture time of about 100 ps is achievable with a CMOS 0.25 μm minimum channel length technology working at low supply voltage.

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