The paper deals with the state of art on the tests for both ΣΔ modulators and ΣΔ Analog to Digital Converters (ADCs). Particular aspects are highlighted concerning the tests for the innovative architectures based on the Band Pass ΣΔ ADC. The analysis of the tests is carried out in conjunction with the discussion about the applicability of the procedures included into the IEEE Standard 1241. Therefore, three fundamental groups of tests are defined: (i) tests according to the IEEE Standard 1241, (ii) tests included into the IEEE Standard 1241 but executed in a different way from the Standard, and (iii) tests pointed out to evaluate the specific characteristics of the ΣΔ modulator not included into the IEEE Standard 1241.

This paper describes a technique mitigating the impact of timing mismatches in timeinterleaved analog-to-digital converters (ADCs). The systems signal-to-noise and distortion ratio (SINAD) and spurious-free dynamic range (SFDR) are increased by controlling the selection order of the channels ADCs in combination with oversampling and consecutive filtering. The proposed method requires only knowledge of the relative level of timing mismatch between the channel ADCs though not the precise magnitude of the mismatch. The impact of timing mismatch on the SINAD and advanced selection ordering schemes are discussed. Moreover, simulation results are presented comparing the figures of merit of existing techniques.

In the last several years, many high-resolution and high-speed ADCs have appeared on the market. Since the signal purity of commercial generators particularly at MHz frequencies has not essentially increased in the same period, the problem of how to test ADCs has rose. This fact initiated the research of alternative methods based on either the application of special signals or posteriori correction of the measured sine-wave signal. The latter method concerning a simple correction in the frequency domain was analyzed, extended and practically applied. The application and the results of this extended method at the frequency of 1 MHz are presented in this paper.

This paper deals with the virtual testing environment for analog-to-digital converters (ADCs) employing a novel and powerful extension of the Servo-Loop method. We build an improved version of the Servo-Loop targeted to full transistor-level circuit simulation of static integral and differential ADC non-linearity. In comparison with the conventional implementation, the Servo- Loop version proposed was enhanced by an effective search algorithm. The algorithm was implemented as a versatile Servo-Looper tool written in Verilog-A language which is suitable for direct co-operation with most of the analog and mixed-signal simulators used in industry. The prospective advantage of our approach is the fact that the implementation in Verilog-A creates an ideal opportunity to build a complex environment comprising the virtual testing engine as well as the DUT in the form of circuit-level ADC design or its behavioral model. At this point, the powerful capabilities of the proposed Servo-Looper tool were successfully confirmed by a large simulation set performed on the ADC behavioral model and the full custom ADC design example. The paper presents the most significant results of the ADC simulation procedure.

This paper demonstrates two methods of noise signal generation for ADC testing. Digital pseudo-random number generator based on LFSR and combinations of LFRS are used. The objective of this exploration is to develop device for generation noise signal with uniformly distributed amplitudes. The signal should be used to measure parameters of AD converters using histogram test method.