IMEKO Event Proceedings Search

Page 547 of 977 Results 5461 - 5470 of 9762

L. Gasparini, D. Macii, M. Gottardi, D. Fontanelli
A LOW-POWER DATA ACQUISITION SYSTEM FOR IMAGE CONTRAST DETECTION

This paper deals with a data acquisition system based on a low-power digital sensor for image contrast detection. This system is suitable for geometric pattern recognition as well as for event monitoring. Possible applications are: surveillance, people access monitoring, and road lines recognition in car-like vehicles. The adopted imager was developed by the Fondazione Bruno Kessler (FBK), Trento, Italy, and it is particularly useful whenever the available energy budget and the channel communication bandwidth are too limited to use common video cameras. Since neither the standard testing procedures for Analog-to-Digital Converters (ADCs) nor those for cameras are suitable to assess the performance of the proposed system, one possible ad-hoc testing methodology is also described and some experimental results are reported.

Miroslav Kamenský, Karol Kovác, Gabriel Války
IMPROVEMENT OF SPECTRAL PROPERTIES OF QUANTIZATION NOISE BY MULTIRESOLUTION QUANTIZATION

In the area of electromagnetic interference (EMI) time-domain EMI measurement systems significantly reduce measurement time. As EMI measurements require high dynamic range or signal-to-noise ratio and wide frequency range, a multiresolution structure of available fast sampling analog-to digital converters (ADC) is used inside such systems. The combination of several ADCs allows to increase overall dynamic range of measuring device. In the paper spectral properties of the quantization noise of system with two ADCs are analyzed by simulations as well as experimentally for harmonic input signal. Multiresolution measurements were realized by two channels of data acquisition card and PC postprocessing. The noise suppression achieved by experiments is presented.

Dominique Dallet, Dario Petri, Daniel Belega
ADCs DYNAMIC TESTING BY MULTIHARMONIC SINE FITTING ALGORITHMS

The paper investigates and compares the performances of two state-of-the-art MultiHarmonic Sine Fitting (MHSF) algorithms when used in the dynamic testing of an Analog-to-Digital Converter (ADC). The influence of the initial estimate of the test signal frequency on the uncertainty of the estimated ADC dynamic parameters is analyzed by using computer simulations. Moreover, the accuracies of the considered MHSF algorithms and the sine-fit algorithms suggested in the existing standards for ADCs testing are compared by means of both computer simulations and experimental results.

Bengt E. Jonsson
AN EMPIRICAL APPROACH TO FINDING ENERGY EFFICIENT ADC ARCHITECTURES

The problem of selecting an optimally efficient ADC architecture at different resolutions is treated using a mainly empirical approach. By analyzing a large amount of measured performance data reported in the literature, the power efficiency of different ADC architectures is investigated. An efficiency hierarchy of ADC architectures is identified, and the low-power enabling features instate-of-the-art designs are summarized. The work shows that there are significant differences between architectures, and also the feasibility of an empirical approach to design optimization.

Serena Porrazzo, Francesco Cannillo, Chris van Hoof
POWER OPTIMIZATION OF HIGH-RESOLUTION LOW-BANDWIDTH SC ΔΣ MODULATORS

This paper presents a procedure for the power-optimal design of high-resolution low-bandwidth switched-capacitor (SC) ΔΣ modulators (ΔΣMs). The most power efficient ΔΣ architecture is identified among single-loop switched-capacitor (SC) feedback (FB) and feed-forward (FF) topologies with different loop order N, oversampling ratio OSR, and quantizer resolution B. Based on the results obtained, an experimental prototype is implemented in a 0.18 µm CMOS process, achieving a signal-to-noise ratio (SNR) of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28 MHz sampling rate and dissipates a total power of 210 µW from a 1.8V supply.

Z. Jelassi, D. Dallet, C. Rebai B. Le Gal, Ch. Jego
AN LCF-ADC MODEL USING CO-SIMULATION TECHNIQUE

Event-driven analog-to-digital conversion, particularly level crossing A/D conversion (LC-ADC), and associated signal reconstruction techniques are still novel approaches that need further improvements to be more efficient in term of energy consumption and bandwidth resources. Among several components, this type of converter is composed of a timer block, which essentially controls the output resolution and reconstructed signal. In this paper, Authors present a level-Crossing Flash ADC (LCF-ADC) model made with Co-simulation technique where Simulink ADC model and HDL timer are associated. Besides, different interpolation algorithms are studied for signal reconstruction.

Salim Alahdab, Reza Lotfi, Wouter A. Serdijn
A 1-V 416-nW FULLY INTEGRATED SENSOR INTERFACE IC FOR PACEMAKERS

An ultra-low-power, low-noise sensor interface IC for pacemakers is presented. The proposed architecture is designed to achieve small chip area and a good trade-off between power consumption and noise figure by using current-mode operation. The IECG signal, from 50 mHz-100 Hz, is first filtered by a bandpass filter. Subsequently, the signal output of the filter is converted into a current by a nonlinear transconductance (Gm) cell. The output of the Gm-cell is digitized by a nonlinear 8-bit 1 kS/s Current-mode Successive Approximation ADC to compensate for the nonlinearity of the Gm-cell. The simulated input-referred noise is 5.48 µVrms, achieving a Noise Efficiency Factor of 3.3, and the simulated power consumption for the overall system is 416 nW while operating from a 1 V supply.

M. Catelani, L. Ciani, S. Giovannetti, A. Zanobini
UNCERTAINTY ANALYSIS IN HIGH-SPEED MULTIFUNCTION DATA ACQUISITION DEVICE

In instrumentation based on an analog-to-digital converter (ADC), the performance of data acquisition (DAQ) device has a direct impact on the performance index of the whole measurement system, so it has an important significance that research the uncertainty analysis of data acquisition board. This paper proposes an automatic measurement system based on DAQ board with automatic uncertainty evaluation of the measurement results according to the “guide to the expression of uncertainty in measurement” and its supplement. Theoretical aspects of the uncertainty analysis in high-speed multifunction data acquisition device and the LabVIEW interface carried out are analyzed and discussed.

Brian Fitzgibbon, Michael Peter Kennedy, Franco Malobertiy
HARDWARE REDUCTION IN DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERS VIA BUS-SPLITTING

This paper discusses a bus-splitting technique for hardware reduction in error feedback digital delta-sigma modulators (DDSMs). The technique is based on error masking and is applied to DDSMs with sinusoidal inputs. We consider the components that contribute to the output signal-to-noise ratio in conventional DDSMs and review new architectures for implementing the digital algorithms without sacrificing performance.

Martin Sekerák, Linus Michaeli, Ján Šaliga, A. Cruz Serra
DYNAMIC DAC TESTING BY REGISTERING THE INPUT CODE WHEN THE DAC OUTPUT MATCHES A REFERENCE SIGNAL

The accuracy of Digital to Analog Converters (DACs) is becoming important proportionally to the requirement on low distortion of the generated signals. This paper presents a new method for measuring the transfer characteristics of high resolution DACs under dynamic condition. The proposed method is based on the comparison of the DAC analog output voltage with a reference signal by using a fast comparator and registration of the DAC digital input code word in the moment when the DAC analog output voltage exceeds the reference voltage. The registration of the digital input code word into a fast memory is controlled by the comparator output. The reference signal is the superposition of the DC voltage generated by the DAC and a slow dithering voltage. Its average value is measured by a precision voltmeter which secures the required metrological accuracy. After digital processing the registered sequence of digital code words is used to determine the Integralnonlinearity (INL) and the Differential-nonlinearity (DNL) of the DAC under test.

Page 547 of 977 Results 5461 - 5470 of 9762