An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF frontend receivers.

In many test and measurement applications, the analogue-to-digital converter (ADC) is the limiting component. Using post-correction methods can improve the performance of the component as well as the over all measurement system. In this paper an ADC is characterised by a Kautz-Volterra (KV) model, which utilises a model-based post-correction of the ADC with general properties and a reasonable number of parameters. Results that are based on measurements on a high-speed 12-bit ADC, shows good results for a third order model.

The paper deals with the state of art on the tests for both ΣΔ modulators and ΣΔ Analog to Digital Converters (ADCs). Particular aspects are highlighted concerning the tests for the innovative architectures based on the Band Pass ΣΔ ADC. The analysis of the tests is carried out in conjunction with the discussion about the applicability of the procedures included into the IEEE Standard 1241. Therefore, three fundamental groups of tests are defined: (i) tests according to the IEEE Standard 1241, (ii) tests included into the IEEE Standard 1241 but executed in a different way from the Standard, and (iii) tests pointed out to evaluate the specific characteristics of the ΣΔ modulator not included into the IEEE Standard 1241.

This paper describes a technique mitigating the impact of timing mismatches in timeinterleaved analog-to-digital converters (ADCs). The systems signal-to-noise and distortion ratio (SINAD) and spurious-free dynamic range (SFDR) are increased by controlling the selection order of the channels ADCs in combination with oversampling and consecutive filtering. The proposed method requires only knowledge of the relative level of timing mismatch between the channel ADCs though not the precise magnitude of the mismatch. The impact of timing mismatch on the SINAD and advanced selection ordering schemes are discussed. Moreover, simulation results are presented comparing the figures of merit of existing techniques.

In the last several years, many high-resolution and high-speed ADCs have appeared on the market. Since the signal purity of commercial generators particularly at MHz frequencies has not essentially increased in the same period, the problem of how to test ADCs has rose. This fact initiated the research of alternative methods based on either the application of special signals or posteriori correction of the measured sine-wave signal. The latter method concerning a simple correction in the frequency domain was analyzed, extended and practically applied. The application and the results of this extended method at the frequency of 1 MHz are presented in this paper.