9762 papers found
The paper provides the analysis of the conversion time of a class of time-to-digital converters based on binary search principle realized by time-to-charge translation and self-timed successive charge redistribution in the binary-scaled capacitor array.
This work surveys various figures-of-merit (FOM) that have been used to evaluate and compare measured ADC performance, and takes a first step towards a systematic classification and analysis. Strengths and weaknesses associated with selected figures-of-merit are discussed, and their potential sweet spots or parametric bias is examined using a combination of theoretical analysis and a near-exhaustive set of scientifically reported experimental data. A commonly used FOM is shown to have a distinct, and highly predictable sweet spot with respect to ENOB, and a strong bias towards scaled...
In the paper, the enhanced version of time-to-digital converter with self-timed successive charge redistribution is presented. In the proposed solution, time-to-charge mapping realized by constant rate charge accumulation is run concurrently to the charge redistribution in the binary-weighted capacitor array. By introducing concurrent charge accumulation and redistribution, the conversion is characterized by reduced conversion time and conversion time jitter, reduction of die area of the chip, and of the number of state transitions per a single conversion cycle.
IEEE Standard 1241-2010 “Terminology and Test Methods for Analog-to-Digital Converters” defines terminology and specifications and describes test methods for measuring the performance of ADC’s. The standard is written for manufacturers and users of ADC’s for use in both static and dynamic applications. The main purpose of this standard is to ensure that manufactures and users of ADC’s have a well-defined set of terms, specifications and test methods so they can understand, describe, and compare the performance of these A/D converters using a common language, with clear definitions....
IEEE Standard 1057-2007 Digitizing Waveform Recorders defines specifications and describes test methods for measuring the performance of electronic digitizing waveform recorders. The latest standard contains many new features not present in the original version. These include new test methods, discussions of requirements for test signals, and new ways of displaying results.
There is a world-wide need to standardize terms, test methods, and the computation of performance parameters for devices that generate, measure, and analyze waveforms. Users need to be able to unambiguously specify the device performance required for particular applications. Manufacturers need to be able to unambiguously state the performance of their devices (e.g., instruments, components, etc.). Metrology facilities need to perform calibrations with well-defined methods to produce reliable data expressed in clear terms. Measurement instruments need to acquire data with well-defined methods...
In the present paper, a continuous time Σ?-Δ converter for biological application is presented. The implemented ASIC has been designed for reading piezo-resistive MEMS cantilever used as DNA detector. The readout channel consists of a first analog front-end circuit able to reduce possible input offset and electronic mismatch, followed by a continuous-time 9b first order Σ?-Δ converter for digital conversion. Simulation results show a circuit accuracy on the measurement of resistance variation in the order of 10 ppm within a maximum range of 10%.
A technique for the digital background calibration of subsampling time-interleaved analog-to-digital converters is proposed. The technique corrects the errors due to gain, offset and timing mismatches among the time-interleaved channels by estimating and nulling the errors with respect to a reference channel through least mean squares loops. Wideband undersampled differentiator filters are exploited thus enabling digital background calibration of timing skews even with wideband input signals outside the first Nyquist band.
A flash Analog to Digital Converter (ADC) at 3 Giga samples per second (GS/s) was developed using QUBIC4X which is a 0.25 µm SiGeC process from NXP Semiconductors. The ADC has a bandwidth close to 1.2 GHz with a resolution of 6-bit. The full design employs a differential structure. The ADC uses a parallel architecture consisting of the following components: track and hold, comparators, and a fat tree encoder. An embedded test system will help us to validate the data transmission, and it is made by a Linear Feedback Shift Register (LFSR). An additive scrambler block allowed us to transmit the...
One of the main parts in the audio uplink path for mobile transceivers is an Analog-to-Digital- Converter (ADC) operating in the audio band. The ADC is usually preceded or followed by a Programmable Gain Amplifier (PGA) which allows, together with a digital signal processor, the gain control of the audio transmit path. Changing the gain is an operation which can lead to artifacts as it inserts discontinuities in the audio wave which behave as distortion sources. This paper describes a novel technique for embedding the gain change in the ADC body. In particular, this technique allows a smooth...